Vertical Semiconductor Nanowires on Metal Substrate

Technology No. 20160145

Photoresist and Etching Fabrication Method

Vertically oriented semiconductor nanowires are created on a metal substrate by a fabrication method that combines photoresist and etching. The simplified photolithography process simplifies nanowire creation and improves precision/control of nanowire density by forming high aspect ratio porous structures with improved side wall quality and high yield. After a developer creates resist patterns, an aluminum layer is etched in regions (patterns) of varying thickness before anodization. This allows nanoporous structures to form on the patterned region at early stages of anodization and grow semiconductor and metal nanowires through the nanopore template so that vertically aligned nanowire arrays or single nanowires with metal or semiconductor materials are realized at the desired areas on metal surface. This new approach does not require a metal oxide mask layer to protect the aluminum layer before an anodization process, and does not require that nanopores be covered before metal nanowire growth.

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Simplified Photolithography Process

Fabricating vertically aligned nanowires is typically done on silicon substrate, while comparable devices on a metal substrate require a complex and expensive chemical vapor deposition process impractical for large area devices. This technology simplifies the process, potentially lowers costs and results in higher yields.


  • Very regular or irregular distribution of vertically aligned semiconductor or metal nanowires on a metal substrate
  • High aspect ratio nanowires
  • High yield: close to 100%
  • 50 nm x 1um aspect ratio
  • Cost effective: requires no metal oxide mask layer; no need to cover nanopores


  • Biological, chemical and nanowire based sensors
  • Photovoltaic cells
  • 3D transistors
  • LED lighting; organic LED performance
  • Field electron devices
  • Next generation computer memory (phase change memory)
  • Semiconductor nanowire solar cell devices

Phase of Development - Prototype: lab has fabricated vertically aligned metal (gold) and semiconductor (silicon) nanowires on metal (platinum) substrate with 50 nm x 1um aspect ratio.

Jeong-Hyun Cho, PhD
Assistant Professor, Department of Electrical and Computer Engineering
External Link (

Patterning Anodic Porous Alumina with Resist Developers for Patterned Nanowire Formation
Material Research Society Online Proceedings Library Archive, Volume 1785 January 2015, pp. 13-18
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