SHE-CRAM: Computational Random Access Memory (CRAM) based on Spin Hall Effect (20180422)

Technology No. 20180422

IP Status: US Patent Application Filed; Application #: 16/803,454

Novel in-memory computation architecture based on spintronic devices provides true in-memory computation

A new Spin Hall effect (SHE) based Computational Random Access Memory (CRAM) technology uses spintronics-based memory arrays to provide true in-memory computation. SHE-CRAM organically enables logic operations within the array and is fast, reliable, features a large noise margin and allows inter-raw communication. SHE-CRAM uses materials with ultra high spin Hall efficiency (such as BiSe and other topological insulators), which allows a low writing voltage and small energy dissipation during computing operations. It also enables a gating control via a three-terminal scheme of the SHE memory cell, providing another degree of freedom for computational operation.

Overcomes memory bottlenecks of current hardware architecture

In modern processor (e.g. CPU) architecture, data is fetched from memory, travels through interconnects, is processed in a logic circuit, and is then stored back into memory. Physically moving data from memory to processor and back introduces significant power consumption and delays, especially for large-scale data analytics applications. Near memory processing (NMP) places the computational unit at the periphery of memory, and while NMP may overcome computational bottlenecks, it does so at a high cost in energy use and delays. By embedding compute capability into the main memory (e.g., realizing “in-memory computation”), the new SHE-CRAM design provides a true in-memory computational platform and effectively addresses these communication bottlenecks. SHE-CRAM is vastly superior to NMP and promises to be a significant improvement over traditional CPU-centric computing. It holds potential applications in future big-data applications and deep neural-network applications, such as pattern recognition, and could also be used in mobile devices and IoT devices requiring low power operations.

Improvements over previous STT-CRAM technology

SHE-CRAM is an extension of the patented STT-CRAM technology described in Case ID 20130219. The previous technology described a similar architecture that provided true in-memory computational operations but was instead based on spin-transfer torque (STT) devices. The new spin Hall effect (SHE)-based CRAM architecture extends and improves the STT-CRAM concept to SHE-based devices for a more competitive approach to conventional CMOS. The unique features and 3T configuration of the SHE memory cell surpass the previous STT-based CRAM by: implementing universal logic gates (NOT, BUFFER, AND, NAND, OR, NOR, MAJ, etc.) due to its much better noise margin offering faster access and more reliable operations through its novel magnetization switching mechanism overcoming the small margin window realizing more universal logic operations offering lower writing voltage and less energy dissipation consuming less energy by using high spin generation materials as the spin Hall channel allowing inter-raw communication not allowed in the STT-based CRAM array addressing current issues with STT-based CRAM and demonstrating better performance

Phase of Development

Proof of concept


  • Relieves bottleneck/energy consumption inherent in communication with memory
  • Three-terminal scheme enables gating control
  • Improvements over STT-based CRAM make it more competitive with CMOS
  • Faster access (current simulations at <100 ps; STT-based CRAM currently at 165 ps)
  • More reliable operation (3 terminal SHE vs. 2 terminal STT)
  • Large noise margin
  • Allows inter-raw communication
  • Low writing voltage
  • Small energy dissipation


  • Spin Hall effect (SHE) based Computational Random Access Memory (CRAM)
  • True in-memory computation
  • Materials with ultra high spin Hall efficiency (such as BiSe and other topological insulators)
  • Three-terminal scheme of SHE memory cell enables gating control


  • Specialized CRAM cores in processors for data centers, mobile devices
  • Non-volatile RAM products
  • Analogous to floating-point units (FPUs) or “math coprocessor” available on a general processor
  • Ideally suited for certain types of fixed and floating point calculations (not floating point addition) in massively parallel operation
  • Big-data applications
  • Deep neural-network applications, such as pattern recognition
  • Mobile devices and IoT devices requiring low power operations

Desired Partnerships

This technology is now available for:
  • License
  • Sponsored research
  • Co-development

Please contact TLO to share your business’ needs and learn more.


Jian-Ping Wang, PhD, Professor, Electrical and Computer Engineering 

Sachin S. Sapatnekar, PhD, Professor, Electrical and Computer Engineering 

Ulya Karpuzcu, PhD, Associate Professor, Electrical & Computer Engineering 

  • swap_vertical_circlelibrary_booksReferences (0)
  • swap_vertical_circlecloud_downloadDownloads (0)
    Files marked with an asterix (*) can only be downloaded by users that have the appropriate product licence. The licence must be active and you must be logged into your account.
Questions about this technology?