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Fast Iterative Decoding of Parallel Concatenated Parity Check Code

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Parallel Parity CheckIterative DecodingEPR4
Jaekyun Moon, PhD
Professor, Electrical Engineering, KAIST University
Managed By
Kevin Nickels
Technology Licensing Officer 612-625-7289
Patent Protection
US Patent 7,143,336
A Low Density Generator Matrix Interpretation of Parallel Concatenated Single Bit Parity Codes
IEEE Transactions on Magnetics, Vol. 37, pp.737-741, Mar. 2001

High Areal Density Magnetic Recording Coding Scheme

A parallel concatenated parity check (PCPC) coding scheme concatenates, in parallel, multiple single bit parity check block codes for high areal density magnetic recording. The low-density generator matrix coding scheme, decoded as a low density parity check code, obtains results using a Lorentzian channel model (with and without transition noise) modeled as first order position jitter. The scheme decreases encoding complexity and increases decoder architecture flexibility while offering signal to noise ratio (SNR) gains over uncoded extended class-4 partial response (EPR4) nearly identical to those using low-density parity-check (LDPC) coding.

Combines TURBO and Low-Density Parity-Check Coding

TURBO coding and low-density parity-check (LDPC) coding, two powerful coding methods, offer large coding gains using practical iterative decoding methods, but each comes with advantages and disadvantages over the other. For example, while encoding TURBO codes is much less complex than encoding LDPC codes, decoding TURBO codes is much more complex than decoding LDPC codes. By concatenating, in parallel, multiple single bit parity check codes using random interleavers, the encoding structure is similar to that for encoding parallel-concatenated turbo codes, except the recursive systematic component codes are replaced with single bit parity check block codes. Decoding from a LDPC perspective considers the parity check matrix corresponding to the encoding structure. This new, parallel concatenated parity check (PCPC) coding scheme combines ideas from both, resulting in a code that is both easy to encode and decode, and also provides increased flexibility in decoding complexity and high-speed hardware implementation tradeoffs.


  • Easier encoding and decoding
  • Nearly identical SNR gains over uncoded EPR4 vs. LDPC coding
  • Concatenates, in parallel, multiple single bit parity check block codes
  • Lorentzian channel model


  • High areal density magnetic recording
  • Data storage systems
  • Data communication systems