Office for Technology Commercialization
http://www.research.umn.edu/techcomm
612-624-0550

Hybrid charge trap transistor-MRAM memory devices

Technology #2020-102

Questions about this technology? Ask a Technology Manager

Download Printable PDF

Image Gallery
Schematic showing cross-sectional view of a charge trap transistor deviceConceptual design of a hybrid charge trap transistor-MRAM device fabricated as a nanowire FET
Categories
Researchers
Jian-Ping Wang, PhD
Professor, Electrical and Computer Engineering
External Link (ece.umn.edu)
Managed By
Doug Franz
Technology Licensing Officer 612-624-0869
Patent Protection

Provisional Patent Application Filed
Designs of hybrid charge trap transistor-MRAM devices for ultra-high-density non-volatile memory.

Applications

  • Non-volatile memory in electronic devices

Key Benefits & Differentiators

  • Usage of flash and MRAM components facilitates
    • write operations independent for one another
    • 2 data bit storage per memory cell
    • high storage density, low power consumption

  • Usage of polycrystalline BiSe makes the designs suitable for CMOS fabrication process

Integrated flash and MRAM device

Prof. Wang’s group at the University of Minnesota has recently demonstrated that sputtered topological insulator field effect transistors (FETs) can be used as charge trap devices. The unique charge-to-spin conversion of topological insulator introduces an opportunity to be integrated with ferromagnets to create hybrid charge trap transistor-Magnetoresistive random-access memory (MRAM) devices. Such hybrid devices, capable of storing 2 data bits in each memory cell - one data bit in the charge trap layer (flash) and another data bit in the ferromagnetic layer (MRAM), paves the way to the development of novel ultra-high-density non-volatile memory.

Four different device designs are conceptualized based on the basic principle of integrating a topological insulator-based charge trap transistor with an MRAM component. Each of these designs present non-trivial 4-state storage, with unique writing and reading techniques (SOT, STT, VCEC) based on their specific operation, stack design, and transport physics. Some of these designs utilize in-plane or perpendicular Magnetic Tunneling Junctions to optimize the read-write operation. These integrated designs boasts advantageous attributes of both flash and MRAM technologies while maintaining CMOS-friendly manufacturing process.

Phase of Development

The charge trap devices has been demonstrated experimentally. The charge trap-MRAM integrated devices are proposed for the first time.

Ready for Licensing

This technology is now available for license! The University is excited to partner with industry to see this innovation reach its potential. Please contact Doug Franz to share your business’ needs and your licensing interests in this technology. The license is for the sale, manufacture or use of products claimed by the patents.