High Voltage Compliance, Output Impedance and Channel Count
A high-voltage, fully-integrated neural stimulator chip for electrical microstimulation features a small chip area and high channel density. Using a feedback-assisted current mirror structure with resource sharing and an efficient chip layout achieves simultaneous high-voltage compliance, high output impedance and high channel count. A foreground current calibration uses a single external capacitor to support the entire stimulation channels, and an active charge-balancing scheme uses a low-resolution SAR ADC (or comparator) to monitor the residual voltage and adapts subsequent stimulation current and timing parameters. A current steering network allows one set of current drivers to support multiple non-concurrent stimulation channels. The chip is designed in a high-voltage process that allows up to 20V power supply and 19V output voltage compliance. A broad range of current mode stimulation waveforms and patterns can be generated, including symmetrical/asymmetrical, biphasic/monophasic, and pulse train stimuli, and the current amplitude, pulse width and stimulation rate are all adjustable. Integrating two complementary charge-balancing techniques reduces residual voltage and stimulation artifacts. The stimulator triggers neural spikes, modulates neuronal firing rates and alters mesoscopic neuronal activity, and can support a wide variety of neuroscience applications requiring electrical microstimulation.
Active Charge Balancing, Smaller and Scalable Design
Previous stimulator designs that achieve high-voltage compliance and high output impedance are unsuitable for implantable devices due to bulky design, low channel count and high power consumption. System-on-chip (SoC) stimulators that employ feedback-assisted current mirror structure and high voltage processes require a large chip area, while off-chip DC blocking capacitors suffer from poor channel density and are difficult to integrate into large-scale stimulator implants. High-channel stimulator SoC are feasible, but because these designs often trade channel density for performance and lack mechanisms to actively monitor residual charge and ensure charge-balancing, they are not suitable for acute microstimulation applications. This new microstimulator chip presents a fully-integrated stimulator with high-voltage compliance, high output impedance, built-in foreground and active charge balancing. The design achieves a good trade-off between high performance and channel density due to adequate resource sharing and efficient chip layout. The smaller and more efficient design is scalable and retains the small chip area and high channel density needed for integration into biomedical implants, particularly large-scale implantable devices with hundreds to thousands of stimulation channels on a millimeter-sized chip area.
BENEFITS AND FEATURES:
- High-voltage, fully-integrated neural stimulator chip for electrical microstimulation
- Efficient chip layout, small chip area and high channel density
- Feedback-assisted current mirror structure
- High output impedance and active charge-balancing
- Generates several current mode stimulation waveforms (e.g., symmetrical/asymmetrical, biphasic/monophasic, and pulse train stimuli)
- Adjustable current amplitude, pulse width and stimulation rate
- Triggers neural spikes, modulates neuronal firing rates and alters mesoscopic neuronal activity
- Neuroscience applications requiring acute electrical stimulation (e.g., vagus nerve stimulation, deep brain stimulation, cortical stimulation)
- Implantable devices
- Neural stimulation instrument manufacturing
- Large-scale, miniaturized biomedical neuromodulation implants
- Neuroprosthetic applications to restore motor and sensory function, neuromuscular stimulation, retinal prosthesis, peripheral nerve stimulation, etc.)
- Neurorepair applications to aid rehabilitation from brain injuries (deep brain stimulation)
- Neurotherapeutic applications to treat nervous system disorders (epilepsy, Alzheimer’s disease, Parkinson’s disease, etc.).
Phase of Development
- First-generation chip: working prototype fabricated and tested; benchtop, in vitro and in vivo results available.
- Second-generation chip: designed and submitted for fabrication; stimulation results available.