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Stochastic Computation without Random Bit Streams Provide Better Results

Technology #20160205-20160379-20160380

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StochasticCircuit
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Researchers
Marc Riedel, PhD
Associate Professor, Electrical and Computer Engineering
External Link (ece.umn.edu)
Managed By
Kevin Nickels
Technology Licensing Officer 612-625-7289
Patent Protection

US Patent Pending 20170255225

US Patent Pending 20170359082
Publications
A Deterministic Approach to Stochastic Computation
International Workshop on Logic and Synthesis, June 10-11, 2016

Uses Deterministic Bit Streams

A disruptive new design methodology, polysynchronous stochastic circuits, recognizes that randomness is not required for stochastic computation. Instead, properly structured deterministic bit streams can be used with the same arithmetic logic. Information is encoded in the duty cycle of pulse-width modulated signals such that the value is digital but the information is analog in time. Performing stochastic computation on analog periodic pulse signals instead of random, stochastic digital bit streams exploits pulse width modulation (PWM) so that time-encoded signals corresponding to specific values are generated by adjusting the frequency and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches, offering savings in area, design and particularly power.

Reduced Latency, Area and Energy Consumption

While stochastic computing has long been a promising technique due to its robustness to noise, significantly simplified logic circuitry and simple hardware requirements, it suffers from high latency and significant overhead (circuit area) in generating pseudorandom bit streams. The hardware necessary for generating pseudorandom bit streams can account for up to 80% of total circuit cost, and despite using low power, the long run-times lead to high latency and energy requirements comparable to conventional binary techniques. This new approach can reduce latency by a factor of 1/2n (where n is the equivalent number of bits of precision). Experimental results on image processing applications have demonstrated 99% performance speed-up, 98% savings in energy dissipation and 40% area reduction comparable to prior stochastic techniques. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.

BENEFITS AND FEATURES:

  • Savings in area, design and particularly power (10’s of %)
  • Compatible with current semiconductor processes + design tools
  • Can be thought of as “analog computation with reliability”
  • Experimental results on image processing applications have demonstrated 99% performance speed-up, 98% savings in energy dissipation and 40% area reduction comparable to prior stochastic techniques
  • Compared to conventional binary, it is slower but has significant reductions in area and energy dissipation
  • Compared to conventional computing, uniform representations provide significant reductions in area/power consumption
  • Compared to stochastic computing, uniform representations provide reduced latency, less area (~90% of area is to generate stochastic sequences), better precision and exact results

APPLICATIONS:

  • Digital and analog chips
  • Image processing
  • Signal processing in general

Phase of Development - Concept: Circuit-level (SPICE) simulations

Interested in Licensing?
The University relies on industry partners to scale up technologies to large enough production capacity for commercial purposes. The license is available for this technology and would be for the sale, manufacture or use of products claimed by the issued patents. Please contact Kevin Nickels to share your business needs and technical interest in this technology and if you are interested in licensing the technology for further research and development.